Graduated Students


  1. Sreepathi Pai Efficient Dynamic Automatic Memory Management and Concurrent Kernel Execution for General-Purpose Programs on Graphics Processing Units , Nov. 2014. (jointly with Prof. Matthew Jacob)
  2. R. Manikantan Improving Last-Level Cache Performance in Single and Multi-Core Processors , Oct. 2013.
  3. Rupesh Nasre Scaling Context-Sensitive Points-to Analaysis, Feb. 2012.
  4. Sandya S. Mannarswamy, Compiler Transformations for Improving the Performance of Software Transactional Memory, Nov. 2011. (jointly with Dr. R. Badrinath, HP IESL, Bangalore)
  5. T.S. Rajesh Kumar, On-Chip Memory Architecture Exploration of Embedded System on Chip, Sep. 2008. (jointly with Dr. C.P. Ravikumar, Texas Instruments India Pvt. Ltd., Bangalore)
  6. Kaushik Rajan, Efficient Cache Organization for Application Specific and General Purpose Processors , May 2008.
  7. V. Santhosh Kumar, Improving the Communication Performance of I/O Intensive and Communication Intensive Application in Cluster Computer Systems , Oct. 2006. (jointly with Prof. Matthew Jacob)


  1. Vaivaswatha N, Fast Flow-Sensitive Pointer Analysis, Aug. 2014.
  2. Prasanna Pandit, Cooperative Execution of OpenCL Programs on Multiple Heterogenous Devices, Nov. 2013
  3. Ashwin Prasad, Automatic Compilation of MATLAB Programs for Synergistic Execution on Heterogeneous Processors, Jan. 2012
  4. Abhishek Udupa,, Efficient Compilation of Stream Programs for Multicores with Accelerators, July 2009.
  5. Aditya Thakur,, Comprehensive Path-sensitive Data-flow Analysis, Aug. 2008.
  6. Girish B.C.,, Efficient Techniques Exploiting Memory Hierarchy to Improve Network Processor Performance , Feb. 2008.
  7. Santosh G. Nagarakatte,, Spill Code Minimization and Buffer and Code Size Aware Instruction Scheduling Techniques , Aug. 2007.
  8. Rajesh Vivekanandham,, Scalable Low Power Issue Queue and Store Queue Design for Superscalar Processors , Dec. 2006.
  9. Sudhakar Surendran , A Systematic Approach to Synthesis of Verification Test-suites for Modular SoC Designs , Nov. 2006. (jointly with Dr. Rubin Parekhji (Texas Instruments India))
  10. Govind S.,, Performance Modeling and Evaluation of Network Processors , July 2006.
  11. K. Shyam, Power-Aware Compilation Techniques for Embedded Systems , July 2006. (jointly with Dr. Milind S. Gandhe (Sasken Corp.))
  12. Sarvani V.V.N.S., Compiler Techniques for Code Size and Power Reduction for Embedded Processors , June 2004.
  13. A. Radhika Sarma , A Simple Replacement Policy and a Dynamic Prefetching Technique for WWW Cache Processors , April 2004.
  14. Subash Chandar G., Reconfigurable Architectures for Application Specific Processors used in Embedded Control Applications, Feb. 2002. (jointly with Dr. Mahesh Mehendale (Texas Instruments India))
  15. K.V. Manjunath, Performance Analysis of Methods that Overcome False Sharing Effects in Software DSMs, Apr. 2001.
  16. N.P. Manoj, CAS-DSM: A Compiler Assisted Software Distributed Shared Memory System, Apr. 1999.
  17. V. Janaki Ramanan, Efficient Resource Usage Modelling, Apr. 1999.
  18. V. Sricharan, Study of Cache and TLB Performance in a Distributed Virtual Shared Memory System, April 1999.
  19. Madhavi G. Valluri, Evaluation of Register Allocation and Instruction Scheduling Methods in Multiple Issue Processors, Jan. 1999.


  1. Patel Arth Kaushebhai, Improving Memory Hierarchy Performance in Heterogeneous System Architecture (HSA), M.E., June 2015.
  2. M. Aravind Krishnan, Large Graph Applications on GPUs, M.Tech., June 2012.
  3. T. Vasu Babu, Incorporating Dynamic Rate Support in StreamIt, M.E., June 2009.
  4. R. Karthikeyan, A Multi-stage Linear Regression Strategy for Determining Rmax of a TOP500 System, M.Tech., July 2008. (jointly with Dr. Sathish Vadhiyar)
  5. R. Manikantan, Performance Enhancement Schemes for Superscalar Processors: Ex ploiting Narrow Width Results and Limited Prefetching, M.E., June 2006
  6. Rajani Pai, FEADS: A Framework for Exploring the Application Design Space on Network Processors, M.E., June 2005
  7. Dushyant M.P. Enhancing the Performance of Clustered Superscalar Processors, M.E., June 2005
  8. S. Sujatha, A Clustered Digital Library Server with Cooperative Semantic Cache, M.Tech., Jan. 2002.
  9. Anand Chitipothu, DOMP: OpenMP Programming on Cluster of SMPs, M.Tech., Jan. 2002.
  10. Vinodh Kumar R. Dynamic Path Profile Aided Recompilation in a Java Just-In-Time Compiler, M.E., Jan. 2001.
  11. S.M. Sandhya, Instruction Scheduling Techniques in SUIF for Value Speculation, M.E., Jan. 2000.
  12. Amit H. Rangari, Implementation of Simple COMA Simulator on R-SIM, M.E., Jan. 2000
  13. Veeral P. Shah, Copy Propagation Optimization and Linear Scan Register Allocation in JIT Compilation, M.E., M.E., Jan. 2000.
  14. Srinivasan R., Compiler Optimizations in the Presence of Value Speculation, M.E.(Int), July 1999.
  15. N. Sreraman, A Vectorizing Compiler for Exploiting Multimedia Extensions, M.E.(Int), July 1999.
  16. V. Amar Nath, Performance Enhancement of Software Disributed Shared Memory, M.E., Jan. 1999.
  17. V. Kumar, Java Virtual Machine: Just-in-Time Compiler Implementation for SPARC, M.E., Jan. 1999
  18. P.S. Udaya Shankara, Granularity Study and Evaluation of Performance Metrics for Shared Memory Accesses in Distributed Shared Memory Architectures , M.E., Jan. 1999.
  19. R. Lakshmi, Performance Enhancement and Evaluation of DSM-SP2: A Distributed Shared Memory, M.E.(Int), July 1997.
  20. B. Hari Krishna, Enhancing the Performance of Multithreaded Architectures, M.E., Jan. 1997.
  21. N.S.S. Narasimha Rao, Implementation of Three Software Pipelining Methods, M.E., Jan. 1997.
  22. S. Ramesh, DSM-SP2: An Implementation of Distributed Shared Memory on IBM SP2, M.E., Jan. 1997.
  23. Biren Gandhi, Distributed Shared Memory on Network of Workstations with TCP/IP, M.E., Jan. 1997.
  24. Amod K. Dani, Software Pipelining for VLIW Architectures , M.E., Jan. 1997.